1. Field of the Invention
The present invention is generally related to the field of semiconductor processing and, more particularly, to a method of making a high performance transistor with a reduced width gate electrode and device incorporating same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
By way of background, an illustrative prior art transistor 1 is depicted in FIG. 1. As shown therein, the transistor 1 is formed in an active region 2 of a semiconducting substrate 3 that is defined by trench isolation regions 7. The transistor 1 generally comprises a gate electrode 3, a gate insulation layer 4, a sidewall spacer 5 and a plurality of source/drain regions 6. The transistor 1 may be fabricated using a variety of known processing techniques. For example, the transistor 1 may be fabricated by forming the trench isolation regions 7 in the substrate 3, and, thereafter, forming the gate electrode 3 and gate insulation layer 4 by forming the appropriate layers of material and patterning those layers using traditional photolithography and etching processes. In one embodiment, the gate insulation layer 4 may be comprised of silicon dioxide, and the gate electrode 3 may be comprised of poly-crystalline silicon (polysilicon). Thereafter, an initial ion implantation process is performed to define extension implant regions within the substrate that are generally self-aligned with respect to the gate electrode 3. Then, the sidewall spacer 5 is formed by depositing an appropriate layer of material, e.g., silicon dioxide, silicon nitride, etc., and thereafter performing an anisotropic etching process. After the spacer 5 is formed, a second ion implantation process, i.e., a source/drain implant, is performed to form source/drain implant regions in the substrate. Thereafter, one or more anneal processes are performed to activate the implanted dopant ions and to repair any damage to the lattice structure of the substrate.
However, one problem with prior art transistor devices, such as the illustrative transistor 1 depicted in FIG. 1, is that, to the extent the extension portions of the source/drain region extend under the gate electrode 3, a capacitor is formed. This capacitor must be charged and discharged on every switching cycle of the transistor 1. This results in delays in the switching speed of the transistor, and in excessive power consumption, a characteristic that is particularly unwanted in portable electronic devices.
The present invention is directed to solving, or at least reducing, some or all of the aforementioned problems.
The present invention is directed to a novel transistor device and a method of making same. In one illustrative embodiment, the transistor comprises a substrate, a gate insulation layer positioned above the substrate, and a gate electrode positioned above the gate insulation layer. The gate electrode is comprised of a layer of polysilicon and a layer of amorphous silicon positioned above the layer of polysilicon, wherein the layer of amorphous silicon has a width that is greater than the width of the layer of polysilicon. The transistor further comprises a source region and a drain region formed in the substrate adjacent the gate electrode.
In one illustrative embodiment, the method disclosed herein comprises forming a gate insulation layer on a semiconducting substrate, forming a layer of polysilicon above the gate insulation layer, forming a layer of amorphous silicon above the layer of polysilicon, and patterning the layer of polysilicon and the layer of amorphous silicon to define a gate structure. The method further comprises reducing the width of the layer of polysilicon and the layer of amorphous silicon by performing an oxidation process, whereby the layer of polysilicon has a post-oxidation width that is less than the post-oxidation width of the layer of amorphous silicon, and forming a plurality of source/drain regions in the substrate adjacent the gate electrode of the device.